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| PRELIMINARY CYP15G0402DX Quad HOTLinkIITM SERDES Features * Second generation HOTLink(R) technology * Fibre-Channel and Gigabit-Ethernet-compliant * 10-bit unencoded data transport -- Aggregate throughput of 12 GB/s * Selectable parity check/generate * Four independently controlled 10-bit channels * Selectable input clocking options * User selectable framing character -- +Comma, comma, or full K28.5 detect -- Single or multicharacter framer for character alignment -- Low-latency option * Synchronous parallel input interface -- User-configurable threshold level -- Compatible with LVTTL, LVCMOS, LVTTL * Synchronous parallel output interface -- Compatible with LVTTL, LVCMOS, LVTTL * 200-to-1500 MBaud serial signaling rate * Internal PLLs with no external PLL components -- Separate clock and data-recovery PLL per channel -- Common transmit clock multiplier PLL * Differential PECL-compatible serial inputs * Differential PECL-compatible serial outputs -- Source matched for 50 transmission lines -- No external resistors required -- Adjustable amplitude for 100 or 150 balanced loads * * * * Compatible with fiber-optic modules and copper cables JTAG boundary scan Built-in self-test (BIST) for at-speed link testing Per-channel Link Quality Indicator -- Analog signal detect -- Digital signal detect * Low-power 3W typical * 256-ball BGA * 0.25 BiCMOS technology Functional Description The CYP15G0402DX Quad HOTLinkIITM SERDES is a point-to-point communications building block allowing the transfer of pre-encoded data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at speeds ranging from 200 to 1500 MBaud per serial link. Each transmit channel accepts pre-encoded 10-bit transmission characters in an input register, serializes each character, and drives it out a PECL-compatible differential line driver. Each receive channel accepts a serial data stream at a differential line receiver, deserializes the stream into 10-bit characters, frames these characters to the proper 10-bit character boundaries, and this data becomes register outputs with a recovered character clock. Figure 1 illustrates typical connections between independent systems and a CYP15G0402DX. As a second-generation HOTLink device, the CYP15G0402DX extends the HOTLink family to faster data rates, while maintaining serial link compatibility with other HOTLink devices. 10 Serial Links 10 Independent Channel Transceiver Independent Channel Transceiver Independent Channel Transceiver Independent Channel Transceiver 10 10 System Host With Encoder/Decoder Cypress Semiconductor Corporation Document #: 38-02023 Rev. *B System Host With Encoder/Decoder 10 10 CYP15G0402DX 10 10 Serial Links 10 10 10 10 Serial Links 10 10 10 10 Serial Links Cable or Optical Connections Figure 1. CYP15G0402DX HOTLink IITM System Connections * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised February 14, 2002 PRELIMINARY CYP15G0402DX The transmit section of the CYP15G0402DX Quad HOTLinkII SERDES consists of four byte wide channels that accept a pre-encoded character on every clock cycle. Transmission characters are passed from the Transmit Input Register to a Serializer. The serialized characters are output from a differential transmission line driver at a bit-rate of 10 or 20 times the input reference clock. The receive section of the CYP15G0402DX Quad HOTLink II SERDES consists of four byte wide channels. Each channel accepts a serial bit-stream from a PECL-compatible differential line receiver and, using a completely integrated PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. Each recovered bit-stream is deserialized and framed into characters. Recovered characters are then passed to the receiver output register, along with a recovered character clock. The LVTTL parallel input interface use different clocking sources to provide flexibility in system architecture. The receive output interface may be configured to output the data with a character-rate or half character-rate clock. Both true and complement recovered-clock outputs are available. Each transmit and receive channel contains independent Built-In Self-Test (BIST) pattern generators and checkers. This BIST hardware allows at-speed testing of the interface data path. HOTLink II devices are ideal for a variety of applications to replace parallel interfaces with high-speed, point-to-point serial links.Some applications include interconnecting backplanes on switches, routers, servers and video transmission systems Transceiver Logic Block Diagram RXDB[9:0] RXDA[9:0] RXDC[9:0] TXDA[9:0] RXDD[9:0] x10 TXDB[9:0] TXDC[9:0] TXDD[9:0] x10 x10 x10 x10 x10 x10 x10 Phase Align Buffer Serializer Framer Phase Align Buffer Serializer Framer Phase Align Buffer Serializer Framer Deserializer Phase Align Buffer Serializer Framer Deserializer Deserializer Deserializer TX RX TX RX TX RX TX RX OUTA INA OUTB INB OUTC INC OUTD Document #: 38-02023 Rev. *B Page 2 of 27 IND PRELIMINARY CYP15G0402DX Transmit Path Block Diagram REFCLK+ REFCLK- = Internal Signal TXRATE SPDSEL TXCLKO+ TXCLKO- Transmit PLL Clock Multiplier Character-Rate Clock Bit-Rate Clock BISTLE BIST Enable Latch Output Enable Latch 8 Phase-Align Buffer BOE[7..0] RBIST[A..D] OELE TXCKSEL TXPERA Input Register 11 11 11 BIST LFSR 4 Parity Check TXDA[0..9] TXOPA Shifter 10 OUTA1+ OUTA1- HML TXLBA TXCLKA TXPERB Phase-Align Buffer BIST LFSR Input Register Shifter Parity Check TXDB[0..9] TXOPB 11 11 11 10 OUTB1+ OUTB1- HML TXLBB TXCLKB TXPERC Phase-Align Buffer Input Register Shifter Parity Check 11 11 11 BIST LFSR 10 OUTC1+ OUTC1- TXDC[0..9] TXOPC HML TXLBC TXCLKC TXPERD Phase-Align Buffer BIST LFSR Input Register Shifter Parity Check TXDD[0..9] TXOPD 11 11 11 10 OUTD1+ OUTD1- HML TXLBD TXCLKD TXRST PARCTL Parity Control Document #: 38-02023 Rev. *B Page 3 of 27 PRELIMINARY CYP15G0402DX Receive Path Block Diagram RXLE BOE[7:0] RX PLL Enable Latch = Internal Signal TRSTZ TMS TCLK TDI TDO LFIA Framer BIST Output Register Shifter RXDA[0..9] RXOPA COMDETA Parity Control Character-Rate Clock SDASEL LPEN INSELA INA1+ INA1- JTAG Boundary Scan Controller Receive Signal Monitor Clock & Data Recovery PLL TXLBA /2 INSELB INB1+ INB1- RXCLKA+ RXCLKA- Receive Signal Monitor Framer Shifter BIST Output Register Clock & Data Recovery PLL LFIB RXDB[0..9] RXOPB COMDETB TXLBB /2 INSELC INC1+ INC1- RXCLKB+ RXCLKB- Receive Signal Monitor Framer BIST Output Register Clock & Data Recovery PLL Shifter LFIC RXDC[0..9] RXOPC COMDETC TXLBC /2 INSELD IND1+ IND1- RXCLKC+ RXCLKC- Receive Signal Monitor BIST Output Register Clock & Data Recovery PLL RBIST[A..D] Framer Shifter LFID RXDD[0..9] RXOPD COMDETD TXLBD /2 FRAMCHAR RXRATE RFEN RFMODE RXCLKD+ RXCLKD- Document #: 38-02023 Rev. *B Page 4 of 27 PRELIMINARY CYP15G0402DX Pin Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A INC- OUTC - N/C N/C VCC IND- OUTD - GND N/C N/C INA- OUTA - GND N/C N/C VCC INB- OUTB - N/C N/C B INC+ OUTC + N/C N/C VCC IND+ OUTD + SDAS EL GND N/C N/C INA+ OUTA + GND N/C N/C VCC INB+ OUTB + N/C N/C C TDI TMS LP ENC LP ENB VCC PAR CTL GND BOE[7] BOE[5] BOE [3] BOE [1 GND GND GND VCC TX RATE RX RATE N/C TDO D TCLK TRSTZ LP END LP ENA VCC RF MODE SPD SEL GND BOE[6] BOE[4] BOE [2] BOE [0] GND GND GND VCC N/C RXLE N/C N/C E VCC VCC VCC VCC VCC VCC VCC VCC F TX PERC TX OPC TXDC [0] RXCK SEL BISTL E RXDB [0] RXOP B RXDB [1] G TXDC [7] TXCK SEL TXDC [4] TXDC [1] GND OELE FRAM CHAR ] RXDB [3] H GND GND GND GND GND GND GND GND J TXDC [9] TXDC [5] TXDC [2} TXDC [3] COMD ETB RXDB [2] RXDB [7] RXDB [4] K RXDC [4] RX CLKC - TXDC [8] LFIC RXDB [5] RX DB[6] RXDB [9] RX CLK B+ L RXDC [5] RX CLKC + TXCLK C TXDC [6] RXDB [8] LFIB RXCL K B- TXDB [6] M RXDC [6] RXDC [7] RXDC [9] RXDC [8] TXDB [9] TXDB [8] TX DB[7] TX CLKB N GND GND GND GND GND GND GND GND P RXDC [3] RXDC [2] RXDC [1] RXDC [0] TXDB [5] TXDB [4] TX DB[3] TX DB[2] R COM DETC RX OPC TX PERD TX OPD TXDB [1] TXDB [0] TX OPB TX PERB T VCC VCC VCC VCC VCC VCC VCC VCC U TXDD [0] TXDD [1] TXDD [2] TXDD [9] VCC RXDD [4] RXDD [3] GND RX OPD RF ENC REFC LK - TXDA [1] GND TXDA [4] TXDA [8] VCC RXDA [4] RX OPA COM DETA RX DA[0] V TXDD [3] TXDD [4] TXDD [8] RX DD[8] VCC RXDD [5] RXDD [1] GND COM DETD RF END REFC LK + RFEN B GND TXDA [3] TXDA [7] VCC RXDA [9] RX DA[5] RX DA[2] RX DA[1] W TXDD [5] TXDD [7] LFID RX CLK D- VCC RXDD [6] RXDD [0] GND TX CLK O- TX RST TX OPA RFEN A GND TXDA [2] TXDA [6] VCC LFIA RX CLK A- RX DA[6] RX DA[3] Y TX DD[6] TX CLKD RXDD [9] RX CLK D+ VCC RXDD [7] RXDD [2] GND TX CLK O+ N/C TX CLKA TX PERA GND TXDA [0] TXDA [5] VCC TXDA [9] RX CLK A+ RX DA[8] RX DA[7] Document #: 38-02023 Rev. *B Page 5 of 27 PRELIMINARY CYP15G0402DX Pin Configuration (Bottom View) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A N/C N/C OUTB OUTB+ INB- VCC N/C N/C GND OUTA OUTA + BOE [1 BOE [0] INA- N/C N/C GND OUTD OUTD+ SDASEL IND- VCC N/C N/C OUTC OUTC + TMS INC- B N/C N/C INB+ VCC N/C N/C GND INA+ N/C N/C GND IND+ VCC N/C N/C INC+ C TDO N/C RX RATE RXLE TX RATE N/C VCC GND GND GND BOE [3] BOE [2] BOE[5] BOE[7] GND PAR CTL SPD SEL RF MODE VCC LP ENB LP ENA VCC LP ENC LP END VCC TDI D N/C N/C VCC GND GND GND BOE[4] BOE[6] GND VCC TRSTZ TCLK E VCC VCC VCC VCC VCC VCC F RXDB [1] RXDB [3] RXOPB RXDB [0] OELE BISTLE RXCKS EL TXDC [1] TXDC [0] TXDC [4] TX OPC TXCK SEL TX PERC TXDC [7] G FRAM CHAR ] GND GND H GND GND GND GND GND GND GND J RXDB [4] RX CLK B+ TXDB [6] TX CLKB GND RXDB [7] RXDB [9] RXDB [2] RX DB[6] COMDE TB RXDB [5] TXDC [3] LFIC TXDC [2} TXDC [8] TXDC [5] RX CLKC RX CLKC+ RXDC [7] GND TXDC [9] RXDC [4] K L RXCLK BTX DB[7] GND LFIB RXDB [8] TXDB [9] GND TXDC [6] RXDC [8] GND TXCLK C RXDC [9] GND RXDC [5] RXDC [6] GND M TXDB [8] GND N P TX DB[2] TX PERB VCC TX DB[3] TX OPB VCC TXDB [4] TXDB [0] VCC TXDB [5] TXDB [1] VCC RXDC [0] TX OPD VCC RXDC [1] TX PERD VCC RXDC [2] RX OPC VCC RXDC [3] COM DETC VCC R T U RX DA[0] RX DA[1] RX DA[3] COM DETA RX DA[2] RX DA[6] RX OPA RX DA[5] RX CLK A- RX CLK A+ RXDA [4] RXDA [9] LFIA VCC TXDA [8] TXDA [7] TXDA [6] TXDA [4] TXDA [3] TXDA [2] GND TXDA [1] RFEN B RFEN A REFCLK REFCLK + TX OPA RF ENC RF END TX RST RX OPD COM DETD TX CLK O- TX CLK O+ GND RXDD [3] RXDD [1] RXDD [0] RXDD [4] RXDD [5] RXDD [6] VCC TXDD [9] RX DD[8] RX CLK D- RX CLK D+ TXDD [2] TXDD [8] LFID TXDD [1] TXDD [4] TXDD [7] TXDD [0] TXDD [3] TXDD [5] V VCC GND GND VCC W VCC GND GND VCC Y RX DA[7] RX DA[8] TXDA [9] VCC TXDA [5] TXDA [0] GND TX PERA TX CLKA N/C GND RXDD [2] RXDD [7] VCC RXDD [9] TX CLKD TX DD[6] Document #: 38-02023 Rev. *B Page 6 of 27 PRELIMINARY CYP15G0402DX Pin Descriptions Quad HOTLink II SERDES Name TXPERA TXPERB TXPERC TXPERD I/O Characteristics LVTTL output, changes following TXCLKO Signal Description Transmit Path Parity Error. Active HIGH parity checking must be enabled and a parity error will be detected. This output is HIGH for one TXCLKO clock period to indicate detection of a parity error in the character presented to the shifter. When parity error is detected, the character in error is replaced with a +C0.7 character to force a corresponding bad character detection at the remote end of the link. This replacement takes place only when parity checking is enabled (PARCTL LOW). When BIST is enabled for a transmit channel, BIST progress is presented on the associated TXPERx output. Once every 511 character times, TXPERx pulses HIGH for one TXCLKO period to indicate a complete pass through the BIST sequence. When the transmit Phase Align Buffers are enabled (TXCKSEL LOW), if an underflow or overflow condition is detected, TXPERx for that channel is asserted and remains asserted until reset by TXRST. Transmit Path Data Signals TXDA[9:0] TXDB[9:0] TXDC[9:0] TXDD[9:0] TXOPA TXOPB TXOPC TXOPD LVTTL input, Transmit Data Inputs. These inputs are captured on the rising edge of the transmit synchronous, interface clock and passed to the transmit shifter. TXDx[9:0] specify the specific transsampled by the mission character to be sent. respective TXCLKx or TXCLKO LVTTL input, Transmit Path Odd Parity. When parity checking is enabled (PARCTL LOW), the synchronous, ODD parity captured at these inputs is XORed with the bits on the associated TXDx bus sampled by the to verify the integrity of the captured character. respective TXCLKx or TXCLKO LVTTL output Transmit Clock Output. This true and complement clock is synthesized by the transmit PLL and is synchronous to the internal transmit character clock. It operates at either the same frequency as REFCLK, or at twice the frequency of REFCLK. TXCLKO is always equal to the VCO bit-clock frequency /10. The TXCLKO+ output rising edges and TXCLKO- falling edges are phase aligned to the rising edges of the REFCLK input. Transmit Clock Phase Reset, active LOW. When LOW, the transmit Phase Align Buffers are allowed to adjust their data transfer timing to allow clean transfer of data from the Input Register to the transmit shifter. When TXRST is HIGH, the internal phase relationship between the selected TXCLKx and the internal character-rate clock is fixed. During this reset alignment period, one or more characters may be added to or lost from all the associated transmit paths as the transmit elasticity buffers are adjusted. Transmit Clock Select. Selects the clock source used to write data into the transmit Input Register. When LOW, all four input registers are clocked by the internal TXCLKO derivative of REFCLK. When TXCKSEL is MID, TXCLKx is used as the input register clock for the associated TXDx[9:0] and TXOPx. When HIGH, TXCLKA is used to clock data into the input register for all channels. Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multiplies REFCLK by 20 to generate the serial bit-rate clock. When TXRATE = LOW, the transmit PLL multiples REFCLK by 10 to generate the serial bit-rate clock. See Table 3 for a list of operating serial rates. When REFCLK is selected for clocking of the receive parallel interfaces, the TXRATE input also determines if the clock on the RXCLKA and RXCLKC outputs is a full or half-rate clock. When TXRATE = HIGH, these clocks are half-rate clocks. When TXRATE = LOW, these output clocks are full-rate clocks and follow the frequency and duty cycle of the REFCLK input. Transmit Path Input Clocks. These inputs are only used when TXCKSEL LOW. These clocks are frequency coherent to TXCLKO, but may be offset in phase. Operating phase is adjusted when TXRST is LOW; and phase locked when TXRST is HIGH. Page 7 of 27 Transmit Path Clock and Control TXCLKO TXRST LVTTL Input, asynchronous TXCKSEL 3-Level Select[1] Static Control Input TXRATE LVTTL Input, asynchronous, internal pull-up TXCLKA TXCLKB TXCLKC TXCLKD LVTTL Clock Input asynchronous, internal pull-up Document #: 38-02023 Rev. *B PRELIMINARY CYP15G0402DX Pin Descriptions Quad HOTLink II SERDES Name RXDA[9:0] RXDB[9:0] RXDC[9:0] RXDD[9:0] COMDETA COMDETB COMDETC COMDETD RXOPA RXOPB RXOPC RXOPD RXRATE I/O Characteristics LVTTL Output, synchronous Signal Description Receive Data Output. These outputs change following the rising edge of the associated RXCLKx clock. Receive Path Data Signals LVTTL Output, synchronous Frame Character Detected. The character in the output register matches that of the selected framing character. Three-state, LVTTL Output Receive Path Odd Parity. When PARCTL isn't low parity generation is enabled, the parity output at these pins is valid for the data on the associated RXDx bus bits. When PARCTL=LOW parity generation is disabled, these output drivers are High-Z. Receive Clock Rate Select. When LOW, the RXCLKx recovered clock outputs are complementary clocks operating at the recovered character rate. Data for the associated receive channels should be latched on the rising edge of RXCLKx+ or falling edge of RXCLKx-. When HIGH, the RXCLKx recovered clock outputs are complementary clocks operating at half the character rate. Data for the associated receive channels should be latched alternately on the rising edge of RXCLKx+ and RXCLKx-. When operating with REFCLK clocking of the received parallel data outputs both RXCKSEL and RXRATE must be LOW. LVTTL Input Static Control Input REFCLK Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit and or single-ended receive PLLs. This input clock may also be selected to clock the transmit and receive LVCMOS input clock parallel interfaces. For an LVCMOS or LVTTL input clock connect clock source to REFCLK to the input pin and float the other REFCLK-. For an LVPECL input level input clock has to be a differential clock, using both inputs. For an LVPECL differential clock, both inputs must have a phase difference of 180 degrees. When TXCKSEL is LOW, a character-rate derivative of REFCLK is used as the clock for the parallel transmit data input interface. 3-Level Select[1], Static Control Input Serial Rate Select. This input specifies the operating bit-rate range of both transmit and receive PLLs. LOW = 200-400 MBaud, MID = 400-800 MBaud, HIGH = 800-1500 MBaud. Differential Serial Data Outputs. These CML outputs are capable of driving terminated transmission lines or standard fiber-optic transmitter modules. SPDSEL Analog I/O and Control OUTA OUTB OUTC OUTD INA INB INC IND SDASEL CML Differential Output LVPECL Differential Differential Serial Data Inputs. These inputs accept the serial data stream for deseriInput alization and decoding. The INx serial stream is fed to the receiver to extract the data and clock content when LPENx is LOW. 3-Level Select[1], static configuration input LVTTL Input, asynchronous, internal pull-down Signal Detect Amplitude Level Select. Allows selection of one of three predefined amplitude trip points for a valid signal indication, as listed in Table 4. Loop-Back-Enable. When HIGH, the transmit serial data from the associated channel is internally routed to its respective receiver clock and data recovery (CDR) circuit. The serial output for the channel where LPENx is active is forced to differential logic-1, and serial data inputs for that channel are ignored. LPENA LPENB LPENC LPEND Document #: 38-02023 Rev. *B Page 8 of 27 PRELIMINARY CYP15G0402DX Pin Descriptions Quad HOTLink II SERDES Name OELE I/O Characteristics LVTTL Input, asynchronous, internal pull-up Signal Description Serial Driver Output Enable Latch Enable. When OELE = HIGH, the signals on the BOE[7:0] inputs directly control the OUTx differential drivers. When the BOE[x] input is HIGH, the associated OUTx differential driver is enabled. When the BOE[x] input is LOW, the associated OUTx differential driver is powered down. When OELE returns LOW, the last values BOE[7:0] are captured. The specific mapping of BOE[7:0] signals to transmit output enables is listed in Table 2. If the device is reset, the latch is reset to enable all outputs. Transmit and Receive BIST Latch Enable. When BISTLE = HIGH, the signals on the BOE[7:0] inputs directly control the transmit and receive BIST enables. When BOE[x] input is LOW, the associated transmit or receive channel is configured to generate or compare the BIST sequence. When the BOE[x] input is HIGH, the associated transmit or receive channel is configured for normal data mode. When BISTLE returns LOW, value present on BOE[7:0] is captured. The specific mapping of BOE[7:0] signals to transmit and receive BIST enables is listed in Table 2. If the device is reset, this enable latch is reset to disable BIST on all transmit and receive channels. Receive Channel Power-Control Latch Enable. When RXLE = HIGH, the signals on the BOE[7:0] directly control the power enables for the receive PLLs and analog logic. When the BOE[7:0] input is HIGH, the all receive channels PLL's and analog logic are active. When the BOE[7:0] input is LOW, all the receive channels are in a power down mode. When RXLE returns LOW, BOE[7:0] values are captured. The specific mapping of BOE[7:0] signals to the associated receive channel enables is listed in Table 2. If the device is reset, the latch is reset to enable all receive channels. BIST, Serial Output, and Receive Channel Enables. These inputs are passed through the output enable latch when OELE is HIGH, and captured in this latch when OELE returns LOW. These inputs are passed through the BIST enable latch when BISTLE is HIGH, and captured in this latch when BISTLE returns LOW. These inputs are passed through the Receive Channel enable latch when RXLE is HIGH, and captured in this latch when RXLE returns LOW. Link Fault Indication Output. Active LOW. LFI* is the logical OR of three internal conditions on the associated channel: 1. received serial data frequency outside expected range; 2. analog amplitude below expected levels; and 3. transition density lower than expected. Test Mode Select. Enables JTAG Test Mode JTAG Test Clock Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not selected. Test Data In. JTAG data input port. Test Reset. JTAG and full chip reset. Active LOW. Initializes the JTAG controller and all other state machines. +3.3V power Signal and power ground for all internal circuits BISTLE LVTTL Input, asynchronous, internal pull-up RXLE LVTTL Input, asynchronous, internal pull-up BOE[7:0] LVTTL Input, asynchronous, internal pull-up LFIA LFIB LFIC LFID JTAG Interface TMS TCLK TDO TDI TRSTZ Power VCC GND LVTTL Output, changes following RXCLKx LVCMOS Input, internal pull-up LVCMOS Input, internal pull-down Three-state LVCMOS Output LVCMOS Input, internal pull-up LVCMOS Input, internal pull-up Document #: 38-02023 Rev. *B Page 9 of 27 PRELIMINARY CYP15G0402DX Name FRAMCHAR I/O Characteristics 3-Level Select[1] Static Control Input Signal Description Framing Character Select. Used to control the type of character used for framing the received data streams. When LOW, the framer looks for an 8-bit positive COMMA character in the data stream. When MID, the framer looks for both positive and negative disparity versions of the 8-bit COMMA character. When HIGH, the framer looks for both positive and negative disparity versions of the K28.5 character. Reframe Mode Select. Used to control the type of character framing system. This signal operates in conjunction with the presently enabled channel bonding mode, and the type of framing character selected. When LOW, the low-latency framer is selected. This will frame on the first occurrence of the selected framing character in the received data stream. This framing mode stretches the recovered clock for multiple cycles to align that clock with the recovered data. When MID, the Cypress-mode multi-byte parallel framer is selected. This requires a pair of the selected framing character, on identical 10-bit boundaries, within a span of 50 bits, before the character boundaries are adjusted. The recovered character clock remains in the same phasing regardless of character offset. When HIGH, the alternate mode multi-byte parallel framer is selected. This requires detection of the selected framing character of the allowed disparities in the received data stream, on identical 10-bit boundaries, on four directly adjacent characters. The recovered character clock remains in the same phasing regardless of character offset. Receive Character Clock. These true and complement clocks are the Receive interface clocks which are used to control timing of data output transfers. These clocks are output continuously at either character rate of 1/20th or 1/10th the serial bit-rate of the input data. Reframe Enable. Active HIGH. When HIGH the framer for the associated channel is enabled to frame as per the framing mode and selected framing character. RFMODE 3-Level Select[1] Static Control Input Receive Path Clock and Clock Control RXCLKA RXCLKB RXCLKC RXCLKD RFENA RFENB RFENC RFEND RXCKSEL Three-state, LVTTL Output clock Static control input LVTTL Input, asynchronous, internal pull-down 3-Level Select[1] Static Control Input Receive Clock Mode. Selects the receive clock-source used to transfer data to the output registers. When LOW, all four output registers are clocked by REFCLK. RXCLKB and RXCLKD outputs are disabled (High-Z), and RXCLKA and RXCLKC present buffered and delayed forms of REFCLK. This clocking mode is required for channel bonding across multiple devices. When MID, each RXCLKx output follows the recovered clock for the respective channel, as selected by RXRATE. When HIGH, and channel bonding is enabled in dual-channel mode (RX modes 3 and 5), RXCLKA outputs the recovered clock from either receive channel A or receive channel B as selected by RXCLKB+, and RXCLKC outputs the recovered clock from either receive channel C or receive channel D as selected by RXCLKD+. These output clocks may operate at the character-rate or half the character-rate as selected by RXRATE. When HIGH and channel bonding is enabled in quad channel mode (RX modes 6 and 8), or if the receive channels are operated in independent mode (RX modes 0 and 2), RXCLKA and RXCLKC output the recovered clock from receive channel A, B, C, or D, as selected by RXCLKB+ and RXCLKD+. This output clock may operate at the character-rate or half the character-rate as selected by RXRATE. Parity Check/Generate Control. Used to control the different parity checks. When LOW, parity checking and generation are disabled, and the RXOPx output drivers are disabled. When MID, the TXDx[9:0] inputs are checked, along with TXOPx, for valid ODD parity, and valid ODD parity is generated for the RXDx[9:0] outputs and presented on RXOPx. When HIGH, the TXDx[9:0] inputs are checked, along with TXOPx, for valid ODD parity. Valid ODD parity is generated for the RXDx[9:0] and COMDETx outputs and presented on RXOPx. Device Control Signals PARCTL 3-Level Select[1], Static Control Input Note: 1. 3-Level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH. The LOW level is usually implemented by direct connection to VSS (ground). The HIGH level is usually implemented by direct connection to VCC (power). When not connected or allowed to float, a 3-Level select input will self-bias to the MID level. Document #: 38-02023 Rev. *B Page 10 of 27 PRELIMINARY CYP15G0402DX CYP15G0402DX HOTLink II SERDES Operation The CYP15G0402DX is designed to support transfer of large quantities of data, using high-speed serial links. This device contains four byte wide channels. CYP15G0402DX Transmit Data Path Data Path The transmit path of the CYP15G0402DX supports four character-wide data paths. These four data paths are internally unencoded and require input data that is encoded for reliable transport. Input Register The bits in the Input Register for each channel have fixed bit assignments, as listed in Table 1. Table 1. Input Register Bit Mapping Signal Name TXDx[0] (LSB) TXDx[1] TXDx[2] TXDx[3] TXDx[4] TXDx[5] TXDx[6] TXDx[7] TXDx[8] TXDx[9] (MSB) TXOPx[3] Each input register captures 10 bits on each input clock cycle. When parity checking is enabled, the TXOPx parity input is also captured in the associated input register. Input Register Clocking The transmit Input Registers can be configured to accept data relative to different clock sources. The selection of the clock source is controlled by TXCKSEL. When TXCKSEL is LOW, the transmit Input Registers capture data synchronous to the TXCLKO a derivative of REFCLK. When TXCKSEL is MID, the rising edge of TXCLK is used to capture the data at the associated TXDx[9:0] and TXOPx inputs. When TXCKSEL is HIGH, the rising edge of TXCLKA is used to capture the data at the associated TXDx[9:0] and TXOPx inputs on all four channels. Bus Weight 2 2 2 0 1 2 10B Name a[2] b c d e i f g h j Phase-Align Buffer Data from the Input Registers is normally routed to the associated Phase-Align Buffer. If the transmit Input Registers are configured to capture data synchronous to REFCLK (TXCKSEL = LOW), the Phase-Align Buffers are bypassed and data is passed directly to the parity check and serializer blocks. When the Input Registers are clocked with REFCLK and TXCKSEL LOW, the Phase-Align Buffers are enabled. These buffers will absorb clock phase differences between the presently selected input clock and the internal character clock. TXRST when low will Initialize the Phase-Align Buffers. When TXRST is returned HIGH, the present input clock phase relative to REFCLK is set. Once set, the input clocks are allowed to skew in time up to half a character period in either direction relative to REFCLK. This time-shift allows the delay paths of the character clocks to change due to operating voltage and temperature, while not affecting operation. Parity Support In addition to the ten data and control bits that are captured at each channel, a TXOPx input is also available on each channel. This allows the CYP15G0402DX to support ODD parity checking for each channel. When PARCTL is LOW, parity checking is disabled. When PARCTL is MID or HIGH, parity is checked on the TXDx[9:0] and TXOPx bits. If parity checking is enabled (PARCTL LOW) and a parity error is detected, the 10-bit character in error is replaced with the 1001111000 pattern an invalid character. Transmit BIST The transmitter interfaces contains an internal BIST pattern generators that can be used to validate both device and link operation. This generator is enabled by the associated BOE[x] signals listed in Table 2 and when BISTLE latch enable input is HIGH. When enabled, a register in the associated transmit channel becomes a pattern generator. This 511-character sequence that includes all Data and Special Character codes, including the explicit violation symbols. This provides a predictable yet pseudo-random sequence that can be matched to an identical receiver. When the BISTLE signal is HIGH, any BOE[x] input that is LOW enables the BIST generator in that associated transmit channel or the BIST checker in the associated receive channel. When BISTLE returns LOW, the values of all BOE[x] signals are captured in the BIST Enable Latch. BIST is disabled following a device reset by TRSTZ. All data and data-control information present at the associated TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is active on that channel. If the receive channels are configured for common clock operation (RXCKSEL MID) each pass is preceded by a 16-character Word Sync Sequence to allow Elasticity Buffer alignment and reset of clock phase. 23 24 2 2 5 6 27 28 29 Notes: 2. LSB is shifted out first. 3. The TXOPx inputs are also captured in the associated input register, but their interpretation is under the separate control of PARCTL. Document #: 38-02023 Rev. *B Page 11 of 27 PRELIMINARY CYP15G0402DX Serial Output Drivers The serial interface Output Drivers make use of differential Current Mode Logic to provide a source-matched driver for the transmission lines. These drivers accept data from the Transmit Shifters. These outputs have signal swings equivalent to that of standard PECL drivers, and are capable of driving AC-coupled optical modules or transmission lines. When configured for internal local loopback test, LPEN = HIGH, the output drivers for all enabled ports are configured to drive a static differential logic-1. Each output can be enabled or disabled separately through the BOE[7:0] inputs, as controlled by the OELE latch-enable signal. When OELE is HIGH, the signals present on the BOE[7:0] inputs are passed through the Serial Output Enable latch to control the serial output drivers. The BOE[7:0] input associated with a specific OUTx driver is listed in Table 2. When OELE is HIGH and BOE[x] is HIGH, the associated serial driver is enabled. When OELE is HIGH and BOE[x] is LOW, the associated driver is disabled and in a power down mode. If both outputs for a channel are disabled, the associated internal logic for that channel is also configured for low power operation. When OELE returns LOW, the values present on the BOE[7:0] inputs are latched in the Output Enable Latch, and remain there until OELE returns HIGH to opened the latch again. Note. When a disabled transmit channel is re-enabled, the data on the serial outputs may not meet all timing specifications for up to 10 ms. Transmit PLL Clock Multiplier The Transmit PLL Clock Multiplier accepts a character-rate or half-character-rate external clock at the REFCLK input, and multiplies that clock by 10 or 20 to generate a bit-rate clock for use by the transmit Shifter. The clock multiplier PLL can accept a REFCLK input between 10 MHz and 150 MHz, however, this clock range of the PLL is controlled by the TXRATE and SPDSEL input signals of the CYP15G0402DX. SPDSEL is a 3-level select[1] (ternary) input that selects one of three operating ranges for the serial data outputs and inputs. The operating serial signalling rate and allowable range of REFCLK frequencies is listed in Table 3. Table 2. Output Enable, BIST, and Receive Channel Enable Signal Map BOE Input BOE[7] BOE[6] BOE[5] BOE[4] BOE[3] BOE[2] BOE[1] BOE[0] Table 3. Operating Speed Settings REFCLK Frequency (MHz) 20 20-40 20-40 40-80 40-75 80-150 800-1500 400-800 Signaling Rate (MBaud) 200-400 Output Controlled (OELE) X OUTD X OUTC X OUTB X OUTA BIST Channel Enable (BISTLE) Transmit D Receive D Transmit C Receive C Transmit B Receive B Transmit A Receive A Receive PLL Channel Enable (RXLE) X Receive D X Receive C X Receive B X Receive A SPDSEL LOW TXRATE 1 0 MID (Open) 1 0 The REFCLK input is a differential input with each input internally biased to 1.5V. If the REFCLK+ input is connected to a TTL, LVTTL, or LVCMOS clock source, the input signal is recognized when the clock signal passes through the internal biased point. When both the REFCLK+ and REFCLK- inputs are connected, the clock source must be a differential clock. This can be either a LVPECL clock, or a differential LVTTL or LVCMOS clock. HIGH 1 0 Document #: 38-02023 Rev. *B Page 12 of 27 PRELIMINARY CYP15G0402DX CYP15G0402DX Receive Data Path Serial Line Receivers A differential line receiver, INx, is on each channel for accepting a serial bit stream. The serial line receiver inputs are differential needing only 100mv pp AC differential input. The input can be DC- or AC-coupled to +3.3V powered fiber-optic interface modules with a ECL/PECL output level. The input could be AC-coupled to +5V powered optical modules. The common-mode tolerance of these line receivers accommodates a wide range of input signals. The local loopback input (LPENx) for each channel allows the serial transmit data for the associated channel to be routed internally back to the clock and data recovery circuit associated with that channel. When a channel is configured for local loopback, the associated transmit serial driver outputs are forced to output a differential logic-1. This prevents local diagnostic patterns from being broadcast to attached remote receivers or optical drivers. Receive Channel Enabled The CYP15G0402DX contains four receive channels that can be independently enabled and disabled. Each channel can be enabled or disabled separately through the BOE[7:0] inputs, as controlled by the RXLE latch-enable signal. When RXLE is HIGH, the signals present on the BOE[7:0] inputs are passed through the Receive Channel Enable latch to control the PLLs and logic of the associated receive channel. The BOE[7:0] input associated with a specific receive channel is listed in Table 2. When RXLE and BOE[x] are HIGH, the associated receive channel is enabled to receive a serial stream from the selected line receiver. When RXLE is HIGH and BOE[x] is LOW, the associated receive channel is disabled and powered down. Signal Detect Each Line Receiver is simultaneously monitored for: * analog amplitude * transition density * received data stream outside normal frequency range (200 ppm). All of these conditions must be valid for the Signal Detect block to indicate a valid signal is present. This status is presented on the LFIx (Link Fault Indicator) output associated with each receive channel. These LFIx outputs change synchronous to the receive interface recovered clock. While the majority of these signal monitors are based on fixed constants, the analog amplitude level detection is adjustable to allow operation with attenuated signals. This adjustment is made through the SDASEL signal, a 3-level select[1] input, which sets the trip point for the detection of a valid signal at one of three levels, as listed in Table 4. SDASEL input controls the analog monitors for all receive channels. Table 4. Analog Amplitude Detect Valid Signal Levels SDASEL LOW MID (Open) HIGH Typical Signal with Peak Amplitudes Above 140 mV p-p differential 280 mV p-p differential 420 mV p-p differential Clock/Data Recovery The extraction of a bit-rate clock and recovery of bits from each received serial stream is performed by a separate Clock/Data Recovery (CDR) block within each channel. The clock extraction function is performed by embedded phase-locked loops that track the frequency and phase of transitions of the incoming bit streams. Each CDR accepts a character-rate or half-character-rate reference clock on the REFCLK input. This REFCLK input is used to ensure that the VCO is operating at the correct frequency. The use of the REFCLK improves PLL acquisition time, and limits the unlocked frequency excursions of the VCO when there is no input data. Regardless of the type of input signal, the CDR will attempt to recover a data stream. If the frequency of the recovered data stream is outside the limits set by the integrated range controls, the PLL reference will switch to REFCLK. When the frequency of the selected data stream returns to a valid frequency, the CDR PLL is allowed to track the received data stream. The frequency of REFCLK is required to be within 200 ppm of the frequency of the clock that drives the REFCLK signal of the remote transmitter to ensure a lock to the incoming data stream. Deserializer/Framer Each CDR circuit extracts bits from the associated serial data stream and clocks these bits into the Shifter/Framer at the bit-clock rate. When enabled, the Framer examines the data stream looking for one or more COMMA or K28.5 characters at all possible bit positions. The location of this character in the data stream is used to determine the frame of the characters that follow. Framing Character The CYP15G0402DX allows selection of one of three combinations of framing characters to support requirements of different interfaces. The selection of the framing character is made through the FRAMCHAR input. FRAMCHAR is a 3-level select [1] input that allows selection of one of three different characters or character combinations. These combinations are listed in Table 5. Table 5. Framing Character Selector Bits Detected in Framer FRAMCHAR LOW MID (Open) HIGH Character Name +COMMA +COMMA -COMMA +K28.5 -K28.5 Bits Detected 00111110XX 00111110XX or 11000001XX 0011111010 or 1100000101 Framer The framer on each channel operates in one of three different modes, as selected by the RFMODE input. When RFMODE is LOW, the low-latency framer is selected. This framer operates by stretching the recovered character clock until it aligns with the character boundaries. In this mode the framer aligns on the first detection of the selected framing character. When RFMODE is MID the Cypress-mode multi-character framer is selected. The detection of multiple framing Page 13 of 27 Document #: 38-02023 Rev. *B PRELIMINARY CYP15G0402DX characters makes the associated link much more robust to incorrect framing. In this mode the framer does not adjust the character clock boundary, but instead aligns the character to the already recovered character clock. This ensures that the recovered clock will not contain any significant phase changes or hops during normal operation. This allows the recovered clock to be distributed to other external circuits. In this framing mode the character boundaries are only adjusted if the selected framing character is detected at least twice within a span of 50 bits, with both instances on identical 10-bit character boundaries. When RFMODE is HIGH, the alternate-mode multi-character framer is enabled. Like Cypress-mode multi-character framing, multiple framing characters must be detected to adjust the character boundaries. In this mode, the data stream must contain a minimum of four of the selected framing characters, received as consecutive characters, before character framing is adjusted. In systems that use 8B/10B coding running disparity rules prohibit the presence of multiple +COMMA characters as consecutive characters, except for the K28.7 comma character. Because of this, the combination of FRAMCHAR LOW and RFMODE HIGH is not recommended. While framing can still take place while following all 8B/10B coding rules, this configuration prevents framing to the normal K28.5 character. Framing is enabled for a channel when the associated RFENx input is HIGH. When RFENx is LOW, the framer for the associated channel is disabled. When a framer is disabled, no changes are made to the recovered character boundaries on that channel, regardless of the presence of framing characters in the data stream. BIST LFSR The output register of each Framer is normally used to pass received characters to the associated output register. When configured for BIST mode, this register becomes a signature pattern generator. When in the BIST mode, a 511-character sequence is generated that includes all Data and Special Character codes, including the explicit violation symbols.This provides a predictable but pseudo-random sequence that can be matched to an identical LFSR in the attached Transmitter(s). When synchronized with the received data stream, the associated receiver checks each character received with each character generated by the LFSR and indicates compare errors and BIST status at the RXDx[2:0] bits of the output register. These generators are enabled by the associated BOE[x] signals listed in Table 2 (when the BISTLE latch enable input is HIGH).When the BISTLE signal is HIGH, any BOE[x] input that is LOW enables the BIST generator/checker in the associated receive channel. When BISTLE returns LOW, the Table 6. BIST Status Bits Status COMDETx RXDx[0] RXDx[1] Priority BIST Mode (RXBISTEN is LOW) 7 BIST Data Compare. Data Character compared correctly. 7 BIST Command Compare. Command Character compared correctly. 2 BIST Last Good. Last Character of BIST sequence detected and valid. 5 Reserved 4 BIST Last Bad. Last Character of BIST sequence was detected invalid. 1 BIST Start. RXBISTEN recognized on this channel, but character compares have not yet commenced. Also presented when the receive PLL is tracking REFCLK instead of the selected data stream. 6 BIST Error. While comparing characters, a mismatch was found in one or more of the decoded character bits. 3 BIST Wait. The receiver is comparing characters. but has not yet found the start of BIST character to enable the LFSR. Description 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 values of all BOE[x] signals are captured in the BIST Enable Latch.These values remain in the BIST Enable Latch until BISTLE is returned high to resample the input again. All captured signals in the BIST Enable Latch are set HIGH and BIST is disabled following a device reset by TRSTZ. The LFSR is initialized by the BIST hardware once the external enable (RXBISTENx) is recognized. The enable resets the BIST LFSR to the BIST-loop start-code of D0.0. D0.0 is sent only at the beginning of the BIST loop. The status of the BIST progress and any character mismatches is appears as an output on the RXDx[2:0] outputs. Code rule violations or running disparity errors the BIST loop will not cause an error indication. RXDx[2:0] indicates 01X for one RXCLK cycle per BIST loop to indicate loop completion. This can be used to check test pattern progress. The specific patterns checked by each receiver are described in detail in the Cypress application note "HOTLink Built-In Self-Test." The sequence compared by the CYP15G0402DX is identical to that in the CY7B933 and CY7C924, allowing interoperable systems to be built when used at compatible serial signalling rates. If a large number of errors are detected, the receive BIST state machine aborts the compare operations and resets the LFSR to look for the start of the BIST sequence again. Power Control The chip can be powered down one channel at a time. The channel to be selected is controlled by BOE[7:0] latch. Both the transmit and the receive channels are controlled by a receive channel power latch and the transmit channel is controlled by an output enable control system. Powering down Document #: 38-02023 Rev. *B Page 14 of 27 PRELIMINARY CYP15G0402DX channels will save considerable power and will reduce system heat generation. Controlling system power dissipation will improve the system reliability. Receive Channel Power-Control Latch Enable. Active HIGH. When RXLE is HIGH, the signals on the BOE[7:0] inputs directly control the power enables for the receive PLLs and analog circuits. When the BOE[7:0] input is HIGH, the associated receive channel [A.D] PLLs and analog logic are active. When the BOE[7:0] input is LOW, the associated receive channel [A.D] PLL's and analog circuits are in a power down mode. When RXLE returns LOW, the last values present on BOE[7:0] are captured. The channels controlled by BOE[7:0] signals are listed in Table 2. When RXLE is HIGH and BOE[x] is HIGH, the associated receive channel is enabled to receive a serial stream from the selected line receiver. When RXLE is HIGH and BOE[x] is LOW, the associated receive channel is disabled and powered down. Any disabled channel will indicate a constant /LFIx output. When a disabled receive channel is re-enabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be indeterminate for up to 10 ms. After powering the chip, the Transmitter may assume either a positive or negative value for its initial running disparity. Upon transmission of any Transmission Character, the transmitter will select the proper version of the Transmission Character When OELE is HIGH and BOE[x] is HIGH, the associated serial driver is enabled. When OELE is HIGH and BOE[x] is LOW, the associated driver is disabled and powered down. If both outputs for a channel are disabled, the internal logic for that channel is powered down. When OELE returns LOW, the values present on the BOE[7:0] inputs are latched in the Output Enable Latch. Table 7. Output Register Bit Assignments [4] Signal Name RXSTx[2] (LSB) RXSTx[1] RXSTx[0] RXDx[0] RXDx[1] RXDx[2] RXDx[3] RXDx[4] RXDx[5] RXDx[6] RXDx[7] (MSB) COMDETx DOUTx[0] DOUTx[1] DOUTx[2] DOUTx[3] DOUTx[4] DOUTx[5] DOUTx[6] DOUTx[7] DOUTx[8] DOUTx[9] Note: 4. The RXOPx outputs are also driven from the associated output register, but their interpretation is under the separate control of PARCTL. Table 8. Output Register Bit Assignments Signal Name RXOPx[5] COMDET[5] RXDx[0] (LSB) RXDx[1] RXDx[2] RXDx[3] RXDx[4] RXDx[5] RXDx[6] RXDx[7] RXDx[8] RXDx[9] (MSB) 5. 6. Bus Weight 10B Name 20 21 22 23 24 2 5 a[6] b c d e i f g h j Output Bus Each receive channel presents a 12-signal output bus consisting of: * a 10-bit data bus * a COMMA detect indicator * a parity bit. The receive decoder assigns the bit values per Table 7. The externally encoded data, the RXDx[0] corresponds to the MSB of the 10 bit data. The signals present on this output bus are shown in Table 8. The framed 10-bit value is presented to the associated Output Register, along with a status output indicating if the character in the output register matches the selected framing characters. The COMDETx status outputs operate the same regardless of the bit combination selected for character framing by the FRAMCHAR input. Characters in Table 5 will cause COMDET assertion, all others characters are mapped to invalid characters. COMDETx is HIGH when the character in the output register of the associated channel contains the selected framing character at the proper character boundary, and LOW for all other bit combinations. When the low-latency framer and half-rate receive port clocking are enabled, RFMODE and RXRATE are both LOW, the framer will stretch the recovered clock to the next 20-bit boundary such that the rising edge of RXCLKx+ occurs when COMDET is present on the associated output bus. Document #: 38-02023 Rev. *B 26 27 2 8 9 2 The RXOPx and COMDETx outputs are also driven from the associated output register, but their generation and interpretation are separate from the data bus. LSB will be shifted in first. When the standard framer is enabled and half-rate receive port clocking are enabled, RFMODE is not low and RXRATE is LOW, the output clock is not modified, but a single pipeline stage may be added or subtracted from the data stream by the framer logic such that the rising edge of RXCLKx+ occurs when COMDET is present on the associated output bus. This adjustment only occurs when the framer for that channel is enabled (RFENx is HIGH). When the framer is disabled, the Page 15 of 27 PRELIMINARY CYP15G0402DX clock boundaries are not adjusted, and COMDETx may be active during the rising edge of RXCLKx-. Parity Generation In addition to the ten data and COMDETx status bits that are output on each channel, an RXOPx output is also available on that channel. The CYP15G0402DX to supports ODD parity generation for each channel. To handle a wide range of system environments, the CYP15G0402DX supports two forms of parity and no parity. * parity on the RXDx[9:0] character * parity on the RXDx[9:0] character and COMDETx status. These modes differ in the number bits which are included in the parity calculation. Only ODD parity is provided which ensures that at least one bit of the data bus is always a logic-1. Those bits covered by parity generation are listed in Table 9. Parity generation is enabled through the 3-level select PARCTL input. When PARCTL is LOW, parity checking is disabled, and the RXOPx outputs are all disabled (High-Z). When PARCTL is MID, ODD parity is generated for the RXDx[9:0] bits. When PARCTL is HIGH, ODD parity is generated for both the RXDx[9:0] bits and the associated COMDETx signal. JTAG Support The CYP15G0402DX contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, only boundary scan is supported. This capability is present only on the LVTTL inputs and outputs and REFCLK. The high-speed serial signals are not part of the JTAG test chain. JTAG ID The JTAG device `0C801069'hex. ID for the CYP15G0402DX is Table 9. Output Register Parity Generation Receive Parity Generate Mode (PARCTL) Signal Name COMDETx RXDx[0] RXDx[1] RXDx[2] RXDx[3] RXDx[4] RXDx[5] RXDx[6] RXDx[7] RXDx[8] RXDx[9] X X X X X X X X X X LOW[7] MID HIGH X[8] X X X X X X X X X X Notes: 7. Receive path parity output drivers are disabled when PARCTL is LOW. 8. When BIST is not enabled,COMDETx is usually driven to a logic 0, but will be driven HIGH when the character in the output buffer is the selected framing character. 3-Level Select Inputs Each 3-Level select input reports as two bits in the scan register. These bits report the LOW, MID, and HIGH state of the associated input as 00, 10, and 11, respectively. Document #: 38-02023 Rev. *B Page 16 of 27 PRELIMINARY CYP15G0402DX Maximum Ratings Above which the useful life may be impaired. For user guidelines, not tested. Storage Temperature -65C to +150C Ambient Temperature with Power Applied-55C to +125C Supply Voltage to Ground Potential-0.5V to +3.8V Output Current into LVTTL Outputs (LOW)30 mA DC Input Voltage--0.5V to VCC+0.5V Static Discharge Voltage> 2000 V (per MIL-STD-883, Method 3015) Latch-Up Current> 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 5% 3.3V 5% CYP15G0402DX DC Electrical Characteristics Over the Operating Range Parameter VOHT VOLT IOST IOZL VIHT VILT IIHT IILT IIHPDT IILPUT Description Output HIGH Voltage Output LOW Voltage Output Short Circuit Current High-Z Output Leakage Current Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Input HIGH Current with internal pull-down Input LOW Current with internal pull-up Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW voltage Common Mode Range Three-Level Input HIGH Voltage Three-Level Input MID Voltage Three-Level Input LOW Voltage Input High Current Input MID Current Input LOW Current Parameter CINTTL CINPECL Description TTL Input Capacitance PECL input Capacitance Min. VCC Max. Min. VCC Max. Min. VCC Max. Vin = Vcc Vin = Vcc/2 Vin = GND Test Conditions TA = 25C, f0 = 1 MHz, VCC = 3.3V TA = 25C, f0 = 1 MHz, VCC = 3.3V -50 REFCLK Input, VIN = VCC Other Inputs, VIN = VCC REFCLK Input, VIN = 0.0V Other Inputs, VIN = 0.0V VIN = VCC VIN = 0.0V Test Conditions IOH = -4 mA, Vcc = Min. IOL = 4 mA, Vcc = Min. VOUT = 0V[9] Min. 2.4 0 -15 -20 2.0 -0.5 Max. VCC 0.4 -35 20 Vcc+0.3 0.8 +1.5 +40 -1.5 -40 +200 -200 Unit V V mA A V V mA A mA A A A LVTTL Compatible Outputs LVTTL Compatible Inputs LVDIFF Inputs: REFCLK VDIFF VIHHP VILLP VCOM VIHH VIMM VILL VIHH VIMM VILL 400 1.0 GND 0.8 0.87 * VCC 0.47 * VCC 0.0 VCC VCC VCC/2 VCC-1.2V VCC 0.53 * VCC 0.13 * VCC 200 50 -200 Max. 7 4 mV V V V V V V A A A Unit pF pF 3-Level Inputs Note: 9. Outputs tested one output at a time, output shorted for less than one second, much less than 10% duty cycle. Document #: 38-02023 Rev. *B Page 17 of 27 PRELIMINARY CYP15G0402DX Differential CML Serial Outputs: OUTA, OUTB, OUTC, OUTD VOHC VOLC VODIF Output HIGH Voltage Output LOW Voltage Output Differential Voltage |(OUT+) - (OUT-)| 100 differential load 150 differential load 100 differential load 150 differential load 100 differential load 150 differential load Typical VCC - 0.5 VCC - 0.5 VCC - 1.1 VCC - 1.1 450 560 Max VCC - 0.2 VCC - 0.2 VCC - 0.7 VCC - 0.7 800 1000 Unit V V V V mV mV Differential Serial Line Receiver Inputs: INA, INB, INC, IND VIDIFF] VIHE VILE IIHE IILE Ivcom[10] Input Differential Voltage |(IN+) - (IN-)| Highest Input HIGH Voltage Lowest Input LOW Voltage Input HIGH Current Input LOW Current Input common mode range VIN = VIHH Max. VIN = VILL Min. ((Vcc-2.0)+.05)min., ((Vcc-.05)max. Commercial Industrial -700 1.25 Typical 860 TBD 3.25 Max. 1100 TBD VCC - 2.0 1000 100 1200 VCC mV V V A A V Unit mA mA Miscellaneous ICC[11] Power Supply Current CYP15G0402DX Transmitter LVTTL Switching Characteristics Over the Operating Range Parameter fTS tTXCLK tTXCLKH tTXCLKL tTXCLKR tTXDS tTXDH fTOS tTXCLKO tTXCLKOD tTXCLKOD tTXODS tTXODH tTXRSS tTXRSH [12] Description TXCLKx Clock Cycle Frequency TXCLKx Period TXCLKx HIGH Time TXCLKx LOW Time TXCLKx Rise Time TXCLKx Fall Time Transmit Data Set-Up Time to TXCLKx (TXCKSEL LOW) Transmit Data Hold Time from TXCLKx (TXCKSEL LOW) TXCLKO Clock Cycle Frequency equals 1x or 2x REFCLK Frequency TXCLKO Period TXCLKOP Duty Cycle Centered with 60 per cent high time TXCLKON Duty Cycle Centered with 40 per cent high time Transmit Data Set-Up Time to TXCLKO (TXCKSEL = LOW) Transmit Data Hold Time from TXCLKO (TXCKSEL = LOW) TXRST Set-Up Time to TXCLKO TXRST Hold Time from TXCLKO Min. 20 6.66 2.2 2.2 0.3 0.3 2 1 20 6.66 -0.7 -0.0 1.5 1.5 3 1 Max. 150 50 Unit MHz ns ns ns 1.7 1.7 ns ns ns ns tTXCLKF[12] 150 50 +0.7 1.5 MHz ns ns ns ns ns ns ns Notes: 10. This is the minimum difference in voltage between the true and the complement input required to ensure detection of a logic 1 or logic 0. A logic true occurs when the input + is above the -input. A logic zero is true when the +input is below the voltage of - input. 11. Maximum current is measured with VCC = MAX, RFEN = LOW, with all serial channels sending a constant alternations 01 pattern, and the output unloaded. Typical is measured under same conditions, except that power is 3.3V. 12. Paralleled data output specifications are only valid if all outputs are loaded with similar DC and AC loads. Document #: 38-02023 Rev. *B Page 18 of 27 PRELIMINARY CYP15G0402DX CYP15G0402DX Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range Parameter tB tRISE Bit Time CML Output Rise Time 20-80% (CML Test Load) [13] Description Condition SPDSEL = HIGH SPDSEL = MID SPDSEL = LOW Min. 5000 50 100 200 50 100 200 Max. 660 270 500 1000 270 500 1000 0.1 0.2 192 Unit ps ps ps ps ps ps ps UI UI ps ns tFALL CML Output Fall Time 80-20% (CML Test Load) [13] SPDSEL = HIGH SPDSEL = MID SPDSEL = LOW tDJ tTJ tTXLOCK Deterministic Jitter (peak-peak) Total Jitter () [15, 17] [14, 17 0.2-1.0Gbps 1.0-1.5Gbps TBD Transmit PLL lock to REFCLK TBD Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range Parameter tRXLOCK tRXUNLOCK tSA tEFW Description Receive PLL Lock to Input Data Stream Receive PLL Lock to Input Data Stream Receive PLL Unlock Rate Static Alignment[16] Error-free Window [14, 17, 18] Min. Max. 10 2500 Unit ms UI ns ps UI TBD 0.75 TBD Notes: 13. REFCLK has no phase or frequency relationship with RXCLK and only acts as a centering reference to reduce clock synchronization time. REFCLK must be within 200- ppm ( 0.02%) of the transmitter PLL reference (REFCLK) frequency, necessitating a 100-ppm crystal. 14. While sending continuous K28.5s, outputs loaded to a balanced 100 load, over the operating range. 15. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating range. 16. Static alignments is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in 3,000 nominal transitions until a character error occurs. 17. Receiver UI is calculated as 1/Fref*10 when RXRATE = LOW if no data is being received of the remote transmitter. If data is being received it is equal to 1/transmit serial bit rate. 18. Error Free Window is a measure of the time window between the bit centers where a transition may occur without causing a sampling error. It is measured over the operational range. Document #: 38-02023 Rev. *B Page 19 of 27 PRELIMINARY CYP15G0402DX HOTLink II Transmitter Switching Waveforms Transmit Interface Write Timing TXCKSEL LOW TXCLKx tTXCLK tTXCLKH tTXCLKL tTXDS TXDx[9:0] TXOPx tTXDH Transmit Interface Write Timing TXCKSEL = LOW TXRATE = LOW REFCLK tREFCLK tREFH tREFL tTREFDS TXDx[9:0], TXOPx tTREFDH Transmit Interface Write Timing TXCKSEL = LOW TXRATE = HIGH REFCLK tREFCLK tREFH Note tTXCLKO tTXOH tTXOL tREFL TXCLKO (internal) tTXODS TXDx[9:0], TXOPx tTXODH tTXODS tTXODH Note: 19. When REFCLK is configured for half-rate operation (TXRATE = LOW) and data is captured using REFCLK instead of a TXCLKx clock (TXCKSEL = LOW), data is captured using the rising edges of the internally synthesized character rate clock. While the rising edge of this clock (TXCLKO) is aligned to the rising edge of REFLCK, it is not aligned to the falling edge of REFCLK. Document #: 38-02023 Rev. *B Page 20 of 27 PRELIMINARY CYP15G0402DX HOTLink II Receiver Switching Waveforms Receive Interface Read Timing RXRATE = LOW RXCLKx+ tRXCLKP tRXCLKH tRXCLKL RXCLKx- tRXDS RXDx[9:0], COMDETx, RXOPx tRXDH Receive Interface Read Timing RXCKSEL = HIGH RXRATE = LOW RXCLKx+ tRXCLKP tRXCLKH tRXCLKL RXCLKx- tRXDS RXDx[9:0], COMDETx, RXOPx tRXDH Static Alignment tB/2- tSA tB/2- tSA Error-Free Window tEFW INA INB tB SAMPLE WINDOW BIT CENTER BIT CENTER INA , INB Document #: 38-02023 Rev. *B Page 21 of 27 PRELIMINARY CYP15G0402DX CYP15G0402DX Receiver LVTTL Switching Characteristics Over the Operation Range Parameter fRS tRXCLKP tRXCLKH tRXCLKL tRXCLKD tRXCLKR[20] tRXCLKF[20] tRXDV-[21] tRXDV+[21] tRXDV-[21] tRXDV+[21] Parameter fREF tREFCLK tREFH tREFL tREFD tREF tREFF tREFDS[21] tREFDH[21] tRREFDA[21] tRREFDV tRREFDVtRREFDV+ tRREFCDVtRREFCDV+ tREFRX REFCLK Period REFCLK HIGH Time (TXRATE = HIGH) REFCLK HIGH Time (TXRATE = LOW) REFCLK LOW Time (TXRATE = HIGH) REFCLK LOW Time (TXRATE = LOW) REFCLK Duty Cycle RXCLKx Rise Time RXCLKx Fall Time Transmit Data Hold Time to REFCLK (TXCKSEL = LOW) Transmit Data Hold Time to REFCLK (TXCKSEL = LOW Receive Data Access Time from REFCLK (RXCKSEL = LOW) Receive Data Valid Time from REFCLK (RXCKSEL = LOW) Receive Data Valid Time from RXCLKA (RXCKSEL = LOW) Receive Data Valid Time from RXCLKA (RXCKSEL = LOW) Receive Data Valid Time from RXCLKC (RXCKSEL = LOW) Receive Data Valid Time from RXCLKC (RXCKSEL = LOW) REFCLK Frequency Referenced to Received Clock Period 4.0 1.5 1.5 3.0 0.5 -0.02 +0.02 2 1 9.5 RXCLKx Period RXCLKx HIGH Time (RXRATE = HIGH) RXCLKx HIGH Time (RXRATE = LOW) RXCLKx LOW Time (RXRATE = HIGH) RXCLKx LOW Time (RXRATE = LOW) RXCLKx Duty Cycle centered with a 50% HIGH Time RXCLKx Rise Time RXCLKx Fall Time Status and Data Valid Time From RXCLKx (RXCKSEL HIGH or MID) Status and Data Valid Time From RXCLKx (RXCKSEL HIGH or MID) Status and Data Invalid Time From RXCLKx (half-rate clock) Status and Data Invalid Time From RXCLKx (half-rate clock) Description RXCLKx Clock Output Frequency Min. 20 6.66 1.5 5 1.5 5 -1.0 0.3 0.3 5UI-1.5 5UI-1.8 5UI-1.0 5UI-2.3 Max. 150 50 24 25 24 25 +1.0 1.2 1.2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns CYP15G0402DXA REFCLK Switching Characteristics Over the Operating Range Description REFCLK Clock Output Frequency Min. 20 6.6 5.9 2.9 5.9 2.9 30 Max. 150 100 24 35 24 35 70 2 2 Unit MHz ns ns ns ns ns % ns ns ns ns ns ns ns ns ns ns % Notes: 20. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested. 21. Parallel data output or input specifications are only valid if all signals are loaded with similar DC and AC loads. Document #: 38-02023 Rev. *B Page 22 of 27 PRELIMINARY CYP15G0402DX Chip Pin Numbers Pin A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 Name INCOUTCNC NC VCC INDOUTDGND NC NC INAOUTAGND NC NC VCC INBOUTBNC NC INC+ OUTC+ NC Type CMLIN CMLOUT POWER CMLIN CMLOUT GND CMLIN CMLOUT GND POWER CMLIN CMLOUT CMLIN CMLOUT Pin D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E01 E02 E03 E04 E17 E18 E19 E20 F01 F02 F03 F04 F17 F18 F19 F20 G01 G02 G03 G04 G17 G18 G19 G20 H01 H02 H03 H04 PIN H17 H18 H19 H20 J01 J02 J03 J04 J17 J18 J19 Name Type TCLK LVTTLIND /TRSTZ LVTTLINU LPEND LVTTLIN LPENA LVTTLIN VCC POWER RFMODE LVLSEL SPDSEL LVLSEL GND GND BOE<6> LVTTLINU BOE<4> LVTTLINU BOE<2> LVTTLINU BOE<0> LVTTLINU GND GND GND GND GND GND VCC POWER NC RXLE LVTTLINU NC NC VCC POWER VCC POWER VCC POWER VCC POWER VCC POWER VCC POWER VCC POWER VCC POWER TXPERC LVTTLOUT TXOPC LVTTLINU TXDC[0] LVTTLIN RXCKSEL LVLSEL BISTLE LVTTLINU RXDB[0] LVTTLOUT RXOPB LTOUT3ST RXDB[1] LVTTLOUT TXDC[7] LVTTLIN XCKSEL LVLSEL TXDC[4] LVTTLIN TXDC[1] LVTTLIN GND GND OELE LVTTLINU FRAMCHAR LVLSEL RXDB[3] LVTTLOUT GND GND GND GND GND GND GND GND NAME TYPE GND GND GND GND GND GND GND GND TXDC[9] LVTTLIN TXDC[5] LVTTLIN TXDC[2] LVTTLIN TXDC[3] LVTTLIN COMDETB LVTTLOUT RXDB[2] LVTTLOUT RXDB[7] LVTTLOUT Page 23 of 27 NC VCC POWER IND+ CMLIN OUTD+ CMLOUT GND GND NC NC INA+ CMLIN OUTA+ CMLOUT GND NC NC VCC POWER INB+ CMLIN OUTB+ CMLOUT NC NC TDI LVTTLINU TMS LVTTLINU LPENC LVTTLIN LPENB LVTTLIN VCC POWER PARCTL LVLSEL SDASEL LVLSEL GND GND BOE<7> LVTTLINU BOE<5> LVTTLINU BOE<3> LVTTLINU BOE<1> LVTTLINU GND GND GND GND GND GND VCC POWER TXRATE LVTTLIND RXRATE LVTTLIND NC TDO LTOUT3ST Document #: 38-02023 Rev. *B PRELIMINARY CYP15G0402DX Pin J20 K01 K02 K03 K04 K17 K18 K19 K20 L01 L02 L03 L04 L17 L18 L19 L20 M01 M02 M03 M04 M17 M18 M19 M20 N01 N02 N03 N04 N17 N18 N19 N20 P01 P02 P03 P04 P17 P18 P19 P20 R01 R02 R03 PIN R04 R17 R18 R19 R20 T01 T02 T03 T04 T17 T18 T19 T20 U01 U02 Name RXDB[4] RXDC[4] RXCLKCTXDC[8] /LFIC RXDB[5] RXDB[6] RXDB[9] RXCLKB+ RXDC[5] RXCLKC+ TXCLKC TXDC[6] RXDB[8] /LFIB RXCLKBTXDB[6] RXDC[6] RXDC[7] RXDC[9] RXDC[8] TXDB[9] TDDB[8] TXDB[7] TXCLKB GND GND GND GND GND GND GND GND RXDC[3] RXDC[2] RXDC[1] RXDC[0] TXDB[5] TXDB[4] TXDB[3] TXDB[2] COMDETC RXOPC TXPERD NAME TXOPD TXDB[1] TXDB[0] TXOPB TXPERB VCC VCC VCC VCC VCC VCC VCC VCC TXDD[0] TXDD[1] Type LVTTLOUT LVTTLOUT LVTTLOUT LVTTLIN LVTTLOUT LVTTLOUT LVTTLOUT LVTTLOUT LVTTLIOD LVTTLOUT LVTTLIOD LVTTLIND LVTTLIN LVTTLOUT LVTTLOUT LVTTLOUT LVTTLIN LVTTLOUT LVTTLOUT LVTTLOUT LVTTLOUT LVTTLIN LVTTLIN LVTTLIN LVTTLIN GND GND GND GND GND GND GND GND LVTTLOUT LVTTLOUT LVTTLOUT LVTTLOUT LVTTLIN LVTTLIN LVTTLIN LVTTLIN LVTTLOUT LTTTLOUT LVTTLOUT TYPE LVTTLINU LVTTLIN LVTTLIN LVTTLINU LVTTLOUT POWER POWER POWER POWER POWER POWER POWER POWER LVTTLIN LVTTLIN Pin U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W01 W02 PIN W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y01 Name TXDD[2] TXDD[9] VCC RXDD[4] RXDD[3] GND RXOPD RFENC REFCLKTXDA[1] GND TXDA[4] TXDA[8] VCC RXDA[4] RXOPA COMDETA RXDA[0] TXDD[3] TXDD[4] TDDD[8] RXDD[8] VCC RXDD[5] RXDD[1] GND COMDETD RFEND REFCLK+ RFENB GND TXDA[3] TXDA[7] VCC RXDA[9] RXDA[5] RXDA[2] RXDA[1] TXDD[5] TXDD[7] NAME /LFID RXCLKDVCC RXDD[6] RXDD[0] GND TXCLKO/TXRST TXOPA RFENA GND TXDA[2] TXDA[6] VCC /LFIA RXCLKARXDA[6] RXDA[3] TXDD[6] Type LVTTLIN LVTTLIN POWER LVTTLOUT LVTTLOUT GND LTOUT3ST LVTTLIND PECLIN LVTTLIN GND LVTTLIN LVTTLIN POWER LVTTLOUT LVTTLOUT LVTTLOUT LVTTLOUT LVTTLIN LVTTLIN LVTTLIN LVTTLOUT POWER LVTTLOUT LVTTLOUT GND LVTTLOUT LVTTLOD3 PECLIN LVTTLOD3 GND LVTTLIN LVTTLIN POWER LVTTLOUT LVTTLOUT LVTTLOUT LVTTLOUT LVTTLIN LVTTLIN TYPE LVTTLOUT LVTTLOUT POWER LVTTLOUT LVTTLOUT GND LVTTLOUT LVTTLINU LVTTLINU LVTTLIN GND LVTTLIN LVTTLIN POWER LVTTLOUT LVTTLOUT LVTTLOUT LVTTLOUT LVTTLIN Page 24 of 27 Document #: 38-02023 Rev. *B PRELIMINARY CYP15G0402DX Pin Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Name TXCLKD RXDD[9] RXCLKD+ VCC RXDD[7] RXDD[2] GND TXCLKO+ NC TXCLKA Type LVTTLIND LVTTLOUT LVTTLIOD POWER LVTTLOUT LVTTLOUT GND LVTTLOUT GND LVTTLIND Pin Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Name TXPERA GND TXDA[0] TXDA[5] VCC TXDA[9] RXCLKA+ RXDA[8] RXDA[7] Type LVTTLOUT GND LVTTLIN LVTTLIN POWER LVTTLIN LVTTLIOD LVTTLOUT LVTTLOUT Ordering Information Speed Standard Standard Ordering Code CYP15G0402DX-BGC CYP15G0402DX-BGI Package Name BL256 BL256 Package Type 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array Operating Range Commercial Industrial Document #: 38-02023 Rev. *B Page 25 of 27 PRELIMINARY Package Diagram 256-lead Thermally Enhanced L2BGA (27 x 27 x 1.52 mm) BL256 CYP15G0402DX 51-85123-*C HOTLink II, and MultiFrame are trademarks of Cypress Semiconductor Corporation. IBM is a registered trademark of International Business Machines. ESCON is a registered trademark of International Business Machines. FICON is a trademark of International Business Machines. Document #: 38-02023 Rev. *B Page 26 of 27 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CYP15G0402DX Document Title: CYP15G0402DX Quad HOTLinkIITM SERDES Document Number: 38-02023 REV. ** *A *B ECN NO. 108363 108915 112986 Issue Date 07/11/01 07/31/01 03/01/02 Orig. of Change TME AMV TPS Description of Change New Data Sheet Changed name of part from PHY to SERDES Changed common mode input specs to match 401D part pp. 17, 18 Added engineering changes to half-rate timing. p. 22 Updated the spec as per meeting with engineering pp. 20-23 Changed the Refclock input to VLTTL both inputs p. 9 Addition of TXCLKO N and the TXCLKO P specs p. 22 Changed the TXCLKO clock output to reflect the new timing p. 22 Changed the Half Clock drawing so that the valid time was at clock edges Changed the input power input p. 21, p. 22 max. power Changed the spec for serial output levels at the different terminations. Changed the common mode input range of serial input Increased the serial input current under the conditions of VCC and min. Added to the duty cycle of transmit and receiver clock signals Changed rise time of the serial inputs and receiver Changed half-rate timing drawing from not valid at clock edges to valid at clock edges Max. voltage reduced from 4.2 to 3.8 Matched the common specs with the family of parts pp. 21-24 Changed max output current to 35 Ma p. 20 Corrected period timing of min. clock from 100 ns to 50 ns p. 19 Added "Preliminary" Added pin RXCKSEL to the pin layout p. 6, 7 to pin layout and pin descriptions Change min. clock frequency Change the front pages Remove decoder command from p. 16, as it is no longer used. Document #: 38-02023 Rev. *B Page 27 of 27 |
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